Phase-locked loop for synchronization with a subcarrier contained in an intelligence signal

ABSTRACT

To ensure that a phase-locked loop locks quickly to the pilot tone of the stereo-multiplex signal when a new transmitter is tuned in, the stereo-multiplex signal is multiplied in a multiplier M by the quadrature component of the pilot tone generated by a digital oscillator, is low-pass-filtered in a low-pass filter, and is fed as a control signal to the oscillator which is composed of a table of length N and a counter for addressing the table entries. The zero phase angle φ 0  is set by a counter offset n 0  by incrementing or decrementing the counter. It is advantageous to employ a virtual table of length N+ which is larger than the length N of the real table. To access the real table, however, only the corresponding MSBs of the actual count n(k) are used which match the address space of the real table of length N.

PRIORITY INFORMATION

This application is a continuation of co-pending Ser. No. 10/096,341filed Mar. 11, 2002.

BACKGROUND OF THE INVENTION

The present invention relates to the field of signal synchronization,and in particular to a phase-locked loop for achieving synchronizationwith a subcarrier contained in an intelligence signal.

DESCRIPTION OF THE RELEVANT ART

VHF radio transmitters such as FM radio stations broadcast astereo-multiplex signal that includes a number of components. Thesecomponents include (i) an audio center signal (also referred to as amono signal) of up to 15 kHz; (ii) a stereo pilot tone at 19 kHz; (iii)a stereo signal in the 23 kHz to 53 kHz band; (iv) a Motorist RadioInformation signal; (v) a narrow-band amplitude-modulated signal at 57kHz; and (vi) a Radio Data System (RDS) signal.

To demodulate the stereo-multiplex signal, synchronization with the 19kHz pilot tone is required which serves as an auxiliary carrier. It isdesirable for this synchronization to occur as quickly as possible eachtime a new transmitter is tuned.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a method for synchronizingwith a subcarrier contained in an intelligence signal comprisesmultiplying the intelligence signal by a quadrature component of asubcarrier to generate a first control signal, low-pass filtering thefirst control signal, and generating the quadrature component of thesubcarrier in response to the low-pass filtered first control signal.

In accordance with another aspect of the invention, a phase-locked loopfor synchronization with a subcarrier contained in an intelligencesignal comprises a digital oscillator having an output at which aquadrature component of the subcarrier is generated in response to acontrol signal. A multiplier includes a first input that receives theintelligence signal and a second input that receives the oscillatoroutput, and generates the control signal. The control signal is theproduct of the intelligence signal and the quadrature component. Alow-pass filter filters the multiplier output to provide a filteredcontrol signal.

In a further aspect of the invention, a phase-locked loop forsynchronization with a subcarrier contained in an intelligence signalmultiplies the intelligence signal by a quadrature component of asubcarrier to generate a control signal, which is filtered and theresultant filtered signal is used to generate the quadrature componentof the subcarrier in response to the low-pass filtered control signal.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of preferred embodiments thereof, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

The FIGURE is a block diagram of a phase-lock loop circuit forsynchronizing with a subcarrier contained in an intelligence signal.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to achieving rapid and precisesynchronization with a subcarrier contained in an intelligence signal.Specifically and in accordance with one embodiment, the presentinvention is directed to synchronizing with an auxiliary carrier of astereo-multiplex signal. In one particular application, the presentinvention is directed to a phase-locked loop circuit and method forsynchronizing with a 19 kHz pilot tone component of a VHFstereo-multiplex signal. The present invention enables a tuner todemodulate the stereo-multiplex signal by quickly synchronizing with thepilot tone component, which serves as an auxiliary carrier for thestereo-multiplex signal. As will be described in detail below withreference to one particular embodiment, a product of the intelligencesignal and a quadrature component of the subcarrier is low-pass filteredand used to control an oscillator to generate the subcarrier quadraturecomponent.

The FIGURE is a schematic block diagram of one embodiment of aphase-locked loop circuit 100 for synchronizing with a subcarriercontained in an intelligence signal. In the exemplary application, theintelligence signal is a stereo-multiplex signal 102. The phase-lockedloop circuit 100 receives the stereo-multiplex signal 102. Thestereo-multiplex signal 102 is presented at the first input of amultiplier 106 whose output 108 is connected with the input of alow-pass filter 110. As will be described in detail below, an oscillator114 generates a quadrature component 104 of the subcarrier of thestereo-multiplex signal 102. In this exemplary application, thequadrature component 104 is the 19 kHz pilot tone component of thestereo-multiplex signal 102 and the quadrature component 104 is appliedto a second input of the multiplier 106. The stereo-multiplex signal 102is multiplied by the quadrature component 104 (i.e., a 19 kHz pilottone) at the multiplier 106 to generate a first control signal 108. Aswill be described in detail below, the first control signal 108 is usedto control the oscillator 114 to generate the quadrature component 104.

The first control signal 108 is provided to the low-pass filter 110which filters the first control signal 108 and provides a filtered firstcontrol signal 112 to control the oscillator 114 to generate thequadrature component 104 as described below. The output of the low passfilter 110 is connected to the input of a loop filter 120, whichgenerates second and third control signals 122, 124, which are describedbelow. The control signals 122, 124 are provided to an oscillatorcontrol circuit 116. In one embodiment, the oscillator 114 is a digitaloscillator and the oscillator control circuit 116 is an arithmetic unit.The oscillator control circuit 116 generates two control signals 126,118 which are used to control the digital oscillator 114 as describedbelow.

In one embodiment, the digital oscillator 114 comprises a look-up table(LUT) of length N and a counter that is configured and arranged toaddress the table entries which are preferably integers of n bits each.The control signal 126 generated by the oscillator control circuit 116is a table address increment value, while the control signal 118 is acounter offset value. The table increment value 126 is used to determinewhich entries in the oscillator table are read while the counter offset118 is provided to the digital oscillator 114 to increment or decrementthe counter to set the zero phase angle φ₀. In one embodiment, a tableentry LUT(n), located at address n, is determined according to equation1:LUT(n)=NINT(2^((nbit−1))·sin(2πn/N)),  (1)where:

n is an integer between 0 and N−1;

N is the length of the table;

nbit is the word length of a table entry; and

NINT signifies rounding to the next higher integer.

As noted, in accordance with one embodiment of the present invention,the quadrature component 104 is the 19 kHz pilot component. The digitaloscillator 114, therefore, preferably generates a sinusoidal quadraturecomponent 104 having a frequency f₀ of 19 kHz. To generate thesinusoidal signal 104 having a frequency of 19 kHz given a scanningfrequency f_(A) of 176.4 kHz, the oscillator table entries are read withan increment Δn 126 that is calculated by the oscillator control circuit116 in accordance with equation 2.Δn=NINT(N·(f ₀ /f _(A)))  (2)Given a table of length N=256, for example, the resulting increment Δnis 110.

As noted, the control signal 118 is a counter offset value that isprovided to the digital oscillator 114 to increment or decrement thecounter to set the zero phase angle φ₀. To set the zero phase angle (φ₀)in the counter, the counter offset 118 is calculated in one embodimentof the digital control circuit 116 according to equation 3:n ₀ =NINT((φ₀/2π)·N)  (3)where n₀ is the counter offset value.

In another embodiment of the invention, the counter offset 118 is atime-variable offset n₀(k). In this embodiment, the count n(k) at timek*T_(A), where T_(A)=1/f_(A), is calculated by equation 4:n(k)=(n(k−1)+Δn+n ₀(k))modulo N(4)

To minimize any accumulation of rounding errors when calculating theaddresses of the table entries, another embodiment provides for avirtual table having a length that is significantly larger than thelength N in the actual table. For example, in one embodiment, the lengthof the virtual table is 64 times as large as the table length N. Allcalculations of counts and addresses are computed based on the aboveequations for the virtual table. To access the real table, however, onlythe corresponding most significant bits of the actual count n(k) areused which match the address space of the real table of length N.

As noted, the first control signal 108 is filtered by the low-passfilter 110. In response to the low-pass-filtered signal 112, the loopfilter 120 generates the control signals 122, 124. The second controlsignal y_(p) 122 is proportional to the first control signal 108. Theloop filter 120 also generates the third control signal y_(i) 124 whichis averaged over time from the first control signal 108. As noted, thecontrol signals 122, 124 are provided to the oscillator control circuit116. In this illustrative embodiment, the oscillator control circuit 116is an arithmetic unit that calculates the offset n₀(k) for the counterof the digital oscillator 114 from the second control signal y_(p) 122and the third control signal y_(i) 124 according to the equation 5:n ₀(k)=NINT(c _(p) ·y _(p)−(N ˜/2π)+ c _(i) y _(i)·(N˜/2π))  (5)In equation 5, the constants c_(p) and c_(i) regulate the controlresponse of the phase-locked loop 100. Based on an appropriate selectionof the constants c_(p) and c_(i), the phase-locked loop 100 may becontrolled in a manner analogous to that of a program identification(PI) controller. Since control of the phase of the pilot tone 104generated by the oscillator 114 is performed via the time-variableoffset n₀(k), a similarly time-variable increment is produced for accessto the table of the counter.

To reduce memory space in the oscillator table, in one embodiment of theinvention a quarter period of a sinusoidal signal is stored. It shouldbe appreciated, however, that with this approach the resultingcalculations of the addresses are more elaborate.

Synchronization of the pilot tone contained in the stereo-multiplexsignal 102 with the pilot tone 104 generated by the digital oscillator114 is achieved as soon as the first control signal 108 becomes zero.This is the case when the quadrature component 104 of the pilot tonegenerated by the oscillator 114 stands in quadrature to the pilot tonecontained in the stereo-multiplex signal 102.

The method according to the invention and the phase-locked loopaccording to the invention are distinguished by the advantage of fastsynchronization. This means that the phase-locked loop according to theinvention locks in quickly. Another advantage of the method according tothe invention is that the method may be implemented through software.

As noted, the present invention can be utilized to achieve rapid andprecise synchronization with a subcarrier contained in an intelligencesignal. In the exemplary application described above, the presentinvention is directed to synchronizing with an auxiliary carrier of aVHF stereo-multiplex signal. As one of ordinary skill in the art wouldappreciate, the synchronization approach of the present invention can beimplemented in conjunction with any tuner now or later developed toenable the tuner to demodulate an intelligence signal such as the notedstereo-multiplex signal. The present invention is particularlywell-suited for stereo radio receivers, specifically car radios.

Although the present invention has been shown and described with respectto several preferred embodiments thereof, various changes, omissions andadditions to the form and detail thereof, may be made therein, withoutdeparting from the spirit and scope of the invention.

1. A method for synchronizing with a subcarrier contained in anintelligence signal, comprising the steps of: multiplying theintelligence signal by a quadrature component of a subcarrier togenerate a first control signal; low-pass filtering the first controlsignal; generating a second control signal proportional to the filteredfirst control signal and a third control signal that is averaged overtime from the filtered first control signal; and generating thequadrature component of the subcarrier in response to the second andthird control signals.
 2. The method of claim 1, where an oscillator isutilized to generate the quadrature component of the subcarrier, wherethe oscillator comprises: a table of length N; and a counter whichserves to access the table entries, the counter having a count beginningat a specified offset and incrementing at a specified increment.
 3. Themethod of claim 2, where the table entries comprise integers of n bitseach.
 4. The method of claim 2, where the step of generating thequadrature component of the subcarrier comprises the step of: readingthe table entries at an increment specified in accordance with thefiltered first control signal.
 5. The method of claim 2, where the stepof generating the quadrature component of the subcarrier comprises thestep of: setting the offset of the counter to cause a phase angle in theoscillator to be set to zero.
 6. The method of claim 4, where the stepof generating the quadrature component of the subcarrier furthercomprises the step of: adjusting the counter by an offset n₀ to set azero phase angle φ₀ in the oscillator prior to reading the tableentries.
 7. The method of claim 2, where the method further comprisesthe step of: forming entries LUT(n) each located at an address n of thetable in accordance with the equationLUT(n)=NINT(2^((nbit−1))·sin(2πn/N)), where n is an integer between 0and N−1; N is the length of the table; nbit is the word length of atable entry; and the operator NINT signifies rounding to the next higherinteger.
 8. The method of claim 4, where the subcarrier quadraturecomponent comprise a sinusoidal signal of frequency f₀ at a scanningfrequency of f_(A), and where the step of reading the table entries at aincrement specified in accordance with the filtered first control signalcomprises the step of: determining the specified increment according tothe equation Δn=NINT(N·(f₀/f_(A))), where operator NINT signifiesrounding to the next higher integer.
 9. The method of claim 5, where thestep of setting the offset of the counter to cause a phase angle in theoscillator to be set to zero comprises the step of: calculating theoffset no of the counter from the zero phase angle φ₀ according to theequation n₀=NINT((φ₀/2π)·N).
 10. The method of claim 5, furthercomprising the step of: calculating a count of the counter at timek*T_(A), where T_(A)=1/f_(A) and f_(A) is the scanning frequency,according to the equation n(k)=(n (k−1)+Δn+n₀(k)) modulo N.
 11. Themethod of claim 2, where the table comprises a length N and where thestep of generating the quadrature component of the subcarrier comprisesthe step of: determining a virtual count offset and increment into avirtual table of length N+ which is larger than the length N of thetable, where the corresponding most significant bits of the actual countn(k) are used to access to the table which match the address space ofthe table of length N.
 12. The method of claim 2, further comprising thesteps of calculating the offset n₀(k) of the counter from the second andthird control signals according to the equationn₀(k)=NINT(c_(p)·y_(p)−(N˜/2π)+c_(i)y_(i)·(N˜/2π)), where c_(p) andc_(i) are constants for regulating the control response.
 13. The methodof claim 1, where a quarter period of a sinusoidal signal is stored. 14.The method of claim 1, where the method is implemented as software. 15.The method of claim 1, where the intelligence signal comprise astereo-multiplex signal, and where the subcarrier comprise a pilot toneat a frequency of 19 kHz.
 16. A phase-locked loop for synchronizationwith a subcarrier contained in an intelligence signal, comprising: anoscillator having an output at which a quadrature component of thesubcarrier is generated; a multiplier having a first input at which theintelligence signal is received and a second input connected to theoutput of the oscillator, and an output at which a first control signalis generated, the first control signal being the product of theintelligence signal and the quadrature component; a low-pass filterhaving an input connected to the multiplier output and an output atwhich a low-pass filtered first control signal is generated; a loopfilter that is responsive to the low-pass filtered first control signal,and generates second and third control signals, where the second controlsignal is proportional to the low-pass filtered first control signal,and the third control signal is averaged over time from the low-passfiltered first control signal; and an oscillator control circuit that isresponsive to the second and third control signals, and provides a pairof additional control signals to the oscillator to control thegeneration of the quadrature component of the subcarrier.
 17. Thephase-locked loop of claim 16, where the oscillator control circuitcomprises an arithmetic unit having first and second inputs at which thesecond and third control signals are received, the arithmetic unithaving first and second outputs connected to the oscillator.
 18. Thephase-locked loop of claim 16, where the oscillator comprises: a tableof length N; and a counter which serves to address the table entries.19. The phase-locked loop of claim 18, where the table entries compriseintegers of n bits each.
 20. The phase-locked loop of claim 18, wherethe table entries are readable with a specified counter increment value.21. The phase-locked loop of claim 18, where a zero phase angle in theoscillator is set by changing the counter by an offset value.
 22. Thephase-locked loop of claim 18, where table entries LUT(n) each locatedat an address n of the table in accordance with the equationLUT(n)=NINT(2^((nbit−1))·sin(2πn/N)), where n is an integer between 0and N−1; N is the length of the table; nbit is the word length of atable entry; and the operator NINT signifies rounding to the next higherinteger.
 23. The phase-locked loop of claim 18, where the subcarrierquadrature component comprise a sinusoidal signal of frequency f₀ at ascanning frequency of f_(A), and where the increment at which the tableentries are read is determined according to the equationΔn=NINT(N·(f₀/f_(A))), where operator NINT signifies rounding to thenext higher integer.
 24. The phase-locked loop of claim 18, where anoffset n₀ of the counter is calculated from a zero phase angle φ₀according to the equation n₀=NINT((φ₀/2π)·N).
 25. The phase-locked loopof claim 18, where the counter increment is calculated at time k*T_(A),where T_(A)=1/f_(A) and f_(A) is the scanning frequency, according tothe equation n(k)=(n(k−1)+Δn+n₀(k))modulo N.
 26. The phase-locked loopof claim 18, where the oscillator control circuit calculates an offsetn₀(k) of the counter from the second and third control signals accordingto the equation n₀(k)=NINT(c_(p)·y_(p)−(N˜/2π)+c_(i)y_(i)·(N˜/2π)),where c_(p) and c_(i) are constants for regulating the control response.27. The phase-locked loop of claim 16, where the intelligence signalcomprises a stereo-multiplex signal, and the subcarrier comprises apilot tone at a frequency of 19 kHz.
 28. (canceled)
 29. (canceled)
 30. Aphase-locked loop for synchronization with a subcarrier contained in anintelligence signal, comprising: an oscillator that generates andprovides a quadrature component of the subcarrier; a multiplier thatmultiples the intelligence signal and the quadrature component, andprovides a first control signal indicative thereof; a low-pass filterthat filters the first control signal and provides a filtered signalindicative thereof; a loop filter that receives the filtered signal andgenerates second and third control signals, where the second controlsignal is proportional to the filtered signal, and the third controlsignal is averaged over time from the filtered signal; and an oscillatorcontrol circuit that is responsive to the second and third controlsignals, and provides a pair of additional control signals to theoscillator to control the generation of the quadrature component.